The demand for improved operational amplifiers, and in particular low voltage, high-speed operational amplifier circuits continues to increase. Such operational amplifier circuits generally include an input stage circuit and an output stage circuit comprised of various amplifier devices and other current sources.
Output stage circuits are generally configured to provide a particular load impedance with a desired output voltage VOUT and current IOUT. The typical main objectives of output stage circuits are to provide negative and positive output currents at high current efficiency, an output voltage range that efficiently uses the full rail-to-rail range, i.e., from the negative supply rail to the positive supply rail, low distortion, and good high-frequency performance. Class-AB biasing is often used to improve performance of output stage circuits due to the ability to eliminate crossover distortion by biasing the output transistors at a small, but finite, current.
With reference to FIG. 1, a conventional class-AB output stage circuit 100 comprises a pair of gate bias voltage circuits 102 and 104 and a class-AB biasing circuit 106 for driving an output buffer 108 comprising output transistors OUT1 and OUT2. Gate bias voltage circuit 102 comprises a pair of diode-connected transistors M1 and M2 coupled to an upper-supply rail VDD and configured with a current source I3 to generate a voltage reference VREF1, and gate bias voltage circuit 104 comprises a pair of diode-connected transistors M3 and M4 coupled to a lower-supply rail VSS and configured with a current source I4 to generate a voltage reference VREF2. Class-AB biasing circuit 106 comprises transistors M5 and M6 configured with current sources I1 and I2 to drive output transistors OUT1 and OUT2, respectively. Gate bias reference voltages VREF1 and VREF2 drive gates of transistors M5 and M6, respectively. The overall speed of output stage circuit 100 is limited by the size of output transistors OUT1 and OUT2; thus, output transistors OUT1 and OUT2 need to be as short as possible, i.e., have short channel lengths, to improve the overall speed and/or capacitive load handling capability.
During operation of output stage circuit 100, as output transistor OUT1 attempts to shut down, and as the gate voltage of transistor M5 approaches voltage reference VREF1, transistor M5 will begin to conduct current, i.e., as the gate of transistor M5 becomes biased, current will begin to flow through transistor M5. However, when such current flows through transistor M5, output transistor OUT1 is prevented from completely shutting down. It is also critical for the various transistors to be suitably matched to facilitate a stable quiescent current, e.g., transistor M1 has to match transistor OUT1 and transistor M2 has to match M5 for the PMOS-side of output stage circuit 100, and transistor M4 has to match transistor OUT2 and transistor M3 has to match M6 for the NMOS-side of output stage circuit 100.
The need for matching arises partly in that the gate-source voltage of transistor M5 plus the gate-source voltage of output transistor OUT1 equals the gate-source voltage of transistor M1 plus the gate-source voltage of transistor M2; however, while the operation of transistors M1 and M2 is a function of constant current source I3, and the operation of transistor OUT1 is a function of its drain-source voltage and Iq (both which vary during operation), the operation of transistor M5 is not a function of output voltage supply. For example, with additional reference to FIG. 2, curves representing drain currents ID of output transistors OUT1 and/or OUT2 versus output voltage VOUT are illustrated. As can be realized, as output voltage VOUT increases, quiescent current Iq changes at an even higher rate, instead of remaining within a desired stable region 202.
Accordingly, a real concern with output stage circuit 100 is that reference voltages VREF1 and VREF2, which dictate operation of transistor M5 within class-AB circuit 106, do not depend on output voltage VOUT or supply rails VDD and VSS. Further, matching between transistors is affected by changes in supply rails VDD and VSS and output voltage VOUT, i.e., as supply rails VDD and VSS change, quiescent current Iq can change as well. This scenario can significantly impact operation of output stage circuit 100 since quiescent current Iq can comprise the majority of the total current budget. Thus, for example, in applications utilizing approximately 0.6 μm processes and requiring minimum-length output transistors OUT1 and OUT2, the change in quiescent current Iq can be more than twice the variation of supply rails VDD and VSS, and even greater, e.g., four times or more, for finer processes requiring even shorter channel lengths for output transistors OUT1 and OUT2.